1. Field of the Invention
This invention relates to digital communication systems, and more particularly to unidirectional source-synchronous digital data transmission systems.
2. Description of the Relevant Art
Digital electronic devices typically communicate via electrical signals (e.g., voltages and/or currents) driven upon electrical conductors (e.g., metal wires). Operations within a digital electronic device transmitting data (i.e., a xe2x80x9csenderxe2x80x9d) may be performed in response to (i.e., synchronized) by a first clock signal, and operations within another digital electronic device receiving the data (i.e., a xe2x80x9creceiverxe2x80x9d) may be synchronized by a second clock signal. In order for the receiver to receive the data correctly and efficiently, the first and second clocks may need to be synchronized such data reception by the receiver occurs in unison with data transmission by the sender.
FIG. 1 is a diagram of a digital communication system 10 employing source-synchronous data transmission. A sender 12 is coupled to a receiver 14 via n data transmission lines 16 and a clock transmission line 18. Sender 12 includes n drivers 20 for driving one end of the n data transmission lines 16 according to binary data signals DATA1 through DATAn, and a driver 22 for driving one end of clock transmission line 18 according to a binary clock signal CLOCK. Sender 12 drives one of two voltage levels upon each of the n data transmission lines 16 dependent upon the logic value of the corresponding binary data signal. Similarly, sender 12 drives one of two voltage levels upon clock transmission line 18 dependent upon the logic value of clock signal CLOCK. Further, sender 12 drives data transmission lines 16 in synchronization with clock signal CLOCK (e.g., in response to a rising or falling transition or xe2x80x9cedgexe2x80x9d of CLOCK).
Receiver 14 includes n comparators 24 coupled to receive the voltage levels driven upon the n data transmission lines 16 by sender 12, and a comparator 26 coupled to receive the voltage levels driven upon clock transmission line 18 by sender 12. Each of the n comparators 24 and comparator 26 also receive a reference voltage level VREF, where reference voltage level VREF is selected to be between the two voltage levels. Comparator 26 produces binary clock signal CLOCK at an output terminal. Receiver 14 also includes n flip-flops 28 receiving the outputs of the n comparators 24 at input terminals and clock signal CLOCK signal at control terminals. As a result, the n flip-flops 28 produce corresponding data signals DATA1 through DATAn in response to the CLOCK signal produced by comparator 26.
As the operating frequencies (i.e., xe2x80x9cspeedsxe2x80x9d) of digital electronic devices increase, electrical conductors used to route signals between components (i.e., signal lines) begin to behave like transmission lines. Transmission lines have characteristic impedances. If the input impedance of a receiving device connected to a transmission line does not match the characteristic impedance of the transmission line, a portion of an incoming signal is reflected back toward a sending device. Such reflections cause the received signal to be distorted. If the distortion is great enough, the receiving device may erroneously interpret the logical value of the incoming signal.
Binary digital signals typically have a low voltage level associated with a logic low (i.e., a logic xe2x80x9c0xe2x80x9d), a high voltage level associated with a logic high (i.e., a logic xe2x80x9c1xe2x80x9d), xe2x80x9crise timesxe2x80x9d associated with transitions from the low voltage level to the high voltage level, and xe2x80x9cfall timesxe2x80x9d associated with transitions from the high voltage level to the low voltage level. A signal line behaves like a transmission line when the signal rise time (or signal fall time) is short with respect to the amount of time required for the signal to travel the length of the signal line (i.e., the propagation delay time of the signal line). As a general rule, a signal line begins to behave like a transmission line when the propagation delay time of the signal line is greater than about one-quarter of the signal rise time (or signal fall time).
Resistive xe2x80x9cterminationxe2x80x9d techniques are often applied to transmission lines, and signal lines long enough to behave like transmission lines, in order to reduce reflections and the resultant signal distortion. One or more electrically resistive elements (e.g., resistors) may be inserted between a driver and an end of a transmission line in order to cause the effective output impedance of the driver to more closely match the characteristic impedance of the transmission line. Similarly, one or more electrically resistive elements may be coupled to an end of a transmission line at a receiver in order to cause the effective input impedance of the receiver to more closely match the characteristic impedance of the transmission line.
FIG. 2 is a diagram of a representative transmission line 30 coupled between sender 12 and receiver 14, wherein resistive terminations are employed in order to reduce signal reflections and distortion within transmission line 30. Transmission line 30 may be one of the n data transmission lines 16 or clock transmission line 18. Switching circuitry 32 within a driver of sender 12 switches a first end of transmission line 30 between a first power supply voltage level VDD and a second power supply voltage level VSS dependent upon a binary input signal (i.e., a binary data signal or binary clock signal CLOCK). It is noted that second power supply voltage level VSS may be a reference ground electrical potential, and VDD may be referenced to VSS. A first termination resistor 34, having a value equal to the characteristic impedance ZO of transmission line 30, is connected between switching circuitry 32 and the first end of transmission line 30 in order to reduce signal reflections and distortion within transmission line 30.
A second end of transmission line 30 is connected a first input terminal of a comparator 36 within receiver 14. A second termination resistor 38, having a value equal to the characteristic impedance ZO of transmission line 30, is connected between the first input terminal of comparator 36 and power supply voltage level VDD in order to reduce signal reflections and distortion within transmission line 30.
When first termination resistor 34 and second termination resistor 38 are coupled to opposite ends of transmission line 30 in order to reduce signal reflections and distortion, they form a voltage divider network which restricts the range of voltage levels which may be used to convey binary signals from sender 12 to receiver 14. FIG. 3 is a graph of voltage levels V present within sender 12 and upon transmission 30 of FIG. 2. When switching circuitry 32 connects the first end of transmission line 30 to VDD through first termination resistor 34, a voltage level equal to VDD exists at the first end transmission line 30. When switching circuitry 32 connects the first end of transmission line 30 to VSS through first termination resistor 34, first termination resistor 34 and second termination resistor 38 are connected in series between VDD and VSS, and a voltage level equal to (VDD/2) exists at the first end transmission line 30 (where VDD is referenced to VSS). As a result, the two voltage levels used to convey binary signals from sender 12 to receiver 14, VDD and (VDD/2), exist only in an upper half of the voltage range between VDD and VSS as shown in FIG. 3. It is noted that a lower half of the voltage range between VDD and VSS is unused due to the use of both first termination resistor 34 and second termination resistor 38.
Reference voltage level VREF, connected to a second input terminal of comparator 36 within receiver 14, is selected between the two voltage levels VDD and (VDD/2) as described above. Voltage values between (VDD/2) and VREF received at the first input terminal of comparator 36 may cause comparator 36 to produce a binary logic 0 signal at an output terminal, and voltage values between VREF and VDD received at the first input terminal of comparator 36 may cause comparator 36 to produce a binary logic 1 signal at the output terminal.
It would be beneficial to have a data transmission system which employs resistive termination of at least one transmission line coupled between a sender and a receiver, and wherein the at least one transmission line is capable of conveying one of k logic states, where k greater than 2. Such increased data transmission capability could be used to reduce a total number of transmission lines coupled between the sender and the receiver, or to increase the rate at which binary data is transmitted from the sender to the receiver via the total number of transmission lines.
A digital communication system is presented which includes at least one transmission line coupled between a first communication device and a second communication device. The transmission line is used to convey binary data from the first communication device to the second communication device. At least one termination resistor, coupled to an end of a transmission line at the second communication device in order to reduce signal reflections and distortion, is also used to generate three or more different voltage levels upon the transmission line dependent upon the binary data. The resulting increase in data transmission capability may be used to reduce the total number of transmission lines coupled between the first and second communication devices, or to increase the rate at which the binary data is transmitted from the first communication device to the second communication device.
In a first embodiment of the digital communication system, the first communication device has an output node coupled to a first end of a transmission line, and the second communication device has an input node coupled to a second end of the transmission line. The second communication device includes a termination resistor coupled between the input node and a power supply voltage level (e.g., VDD). The second communication device may be configured such that an electrical voltage level existing at the input node is substantially dependent upon an amount of electrical current flowing through the termination resistor. The termination resistor may have a value substantially equal to a characteristic impedance of the transmission line such that signal reflections and distortion occurring within the transmission line are substantially reduced.
The first communication device drives the output node in one of p drive states, where pxe2x89xa73. Each of the p drive states causes a different amount of electrical current to flow through the termination resistor such that a different electrical voltage level exists at the input node in each of the p drive states. The different electrical voltage levels existing at the input node in each of the p drive states may differ by substantially equal amounts, and may be associated with different logic levels. The three or more logic levels represent an increase in data transmission capability over the two logic levels used in binary data transmission.
The first communication device may include an output section receiving binary data and driving the output node in one of the p drive states dependent upon the binary data. The output section may also receive a first clock signal, and may drive the output node in response to the first clock signal. The second communication device may include an input section coupled to the input node and configured to produce the binary data from the different electrical voltage levels existing at the input node. The input section may produce the binary data in response to a second clock signal. The first and second clock signals may be synchronized in one of several possible ways in order to achieve synchronous data transmission. For example, the first communication device may provide the first clock signal to the second communication device via a dedicated clock transmission line. Alternately, the second communication device may generate the second clock signal in synchronization with voltage level transitions present upon the transmission line conveying data.
In a second embodiment of the digital communication system, the second communication device may include two termination resistors: a first termination resistor coupled between the input node and the first power supply voltage level (e.g., VDD), and a second termination resistor coupled between the input node and a second power supply voltage level (e.g., VSS). The second communication device may be configured such that an electrical voltage level existing at the input node is substantially dependent upon an amount of electrical current flowing through the first termination resistor. The first and second termination resistors may have values substantially equal to twice the characteristic impedance of the transmission line such that the transmission line is terminated in the characteristic impedance of the transmission line, and signal reflections and distortion occurring within the transmission line are substantially reduced.
The first communication device may include drive circuitry within the output section. The output section may electrically couple the drive circuitry to the output node inp drive states, where pxe2x89xa72, and drive the output node in the p drive states via the drive circuitry. The output section may not drive the output node in an additional xe2x80x9cnon-drivexe2x80x9d state. In the non-drive state, the output section may electrically decouple the drive circuitry from the output node. In each of the p drive states and the non-drive state, a different amount of electrical current may flow through the first termination resistor such that a different electrical voltage level exists at the input node. The different electrical voltage levels existing at the input node in each of the p drive states and the non-drive state may differ by substantially equal amounts and may be associated with different logic levels.
In the second embodiment, the drive circuitry may drive the output node in one of the p drive states dependent upon the binary data and in response to the first clock signal. The output section may also electrically decouple the drive circuitry from the output node in the non-drive state dependent upon the binary data and in response to the first clock signal. As described above, the second communication device may include an input section coupled to the input node and configured to produce the binary data from the different electrical voltage levels existing at the input node. The input section may produce the binary data in response to a second clock signal. The first and second clock signals may be synchronized as described above in order to achieve synchronous data transmission.
In a third embodiment of the digital communication system, the first communication device has m data output nodes and a clock output node. The second communication device has m data input nodes corresponding to the m data output nodes, and a clock input node corresponding to the clock output node. In the third embodiment, the digital communication system includes m data transmission lines coupled between the corresponding m data output nodes and m data input nodes, and a clock transmission line coupled between the clock output and input nodes.
The second communication device includes an input section having m+1 termination resistors. Each of m of the termination resistors is coupled between a different one of the m data input nodes and a power supply voltage level (e.g., VDD), and the remaining termination resistor is coupled between the clock input node and the power supply voltage level. The second communication device may be configured such that: (i) an electrical voltage level existing at a given data input node is substantially dependent upon an amount of electrical current flowing through the termination resistor coupled between the given data input node and the power supply voltage level, and (ii) an electrical voltage level existing at the clock input node is substantially dependent upon an amount of electrical current flowing through the termination resistor coupled between the clock input node and the power supply voltage level. Each termination resistor may have a value substantially equal to a characteristic impedance of a corresponding transmission line such that signal reflections and distortion occurring within the corresponding transmission line are substantially reduced.
In the third embodiment, the first communication device includes an output section coupled to receive n binary data signals and a binary clock signal. The output section drives each of the m data output nodes in one of p drive states dependent upon the n binary data signals and in response to the binary clock signal, where n greater than m and pxe2x89xa73. Each of the p drive states used to drive a given data output node causes a different amount of electrical current to flow through the termination resistor coupled to the corresponding data input node such that a different electrical voltage level exists at the corresponding data input node in each of the p drive states. The different electrical voltage levels existing at the corresponding input node in each of the p drive states may differ by substantially equal amounts and may be associated with different logic levels.
The output section also drives the clock output node in one of q drive states dependent upon the binary clock signal, where qxe2x89xa72. Each of the q drive states causes a different amount of electrical current to flow through the termination resistor coupled to the clock input node such that a different electrical voltage level exists at the clock input node in each of the q drive states. The different electrical voltage levels existing at the clock input node in each of the q drive states may be associated with different logic levels.
The input section is configured to: (i) produce the binary clock signal from the electrical voltage levels existing at the clock input node, and (ii) produce the n binary data signals from the electrical voltage levels existing at the m data input nodes in response to the binary clock signal.
The n binary data signals simultaneously convey one of 2n logical states. The m data transmission lines having one of p voltage levels present thereupon simultaneously convey one of pm logical states. Thus the minimum value of m for simultaneous conveyance of the one of 2n logical states is the smallest integer greater than or equal to logp(2n). For example, n and p may both equal 3. In this case, log3(23) is approximately 1.89, and the minimum value of m for simultaneous conveyance of one of 23 (8) logical states is 2, the smallest integer greater than or equal to 1.89.
In a fourth embodiment of the digital communication system, the first communication device again has m data output nodes and a clock output node, and the second communication device has m data input nodes corresponding to the m data output nodes and a clock input node corresponding to the clock output node. A total of m data transmission lines are coupled between corresponding data input and output nodes, and a clock transmission line is coupled between the clock input node and the clock output node.
In the fourth embodiment, the second communication device includes an input section having; (i) a first m termination resistors each coupled between a different one of the m data input nodes and a first power supply voltage level (e.g., VDD), (ii) a second m termination resistors each coupled between a different one of the m data input nodes and a second power supply voltage level (e.g., VSS), and (iii) a termination resistor coupled between the clock input node and the first power supply voltage level. The second communication device may be configured such that: (i) an electrical voltage level existing at a given data input node is substantially dependent upon an amount of electrical current flowing through the termination resistor coupled between the given data input node and the first power supply voltage level, and (ii) an electrical voltage level existing at the clock input node is substantially dependent upon an amount of electrical current flowing through the termination resistor coupled between the clock input node and the first power supply voltage level. Each of the two termination resistors coupled to a given data input node may have a value substantially equal to twice a characteristic impedance of a data transmission line coupled to the input node such that the data transmission line is terminated in its characteristic impedance. As a result, signal reflections and distortion occurring within the m data transmission lines are substantially reduced.
As in the third embodiment, the first communication device includes an output section coupled to receive n binary data signals and a binary clock signal. In the fourth embodiment, the output section may drive each of the m data output nodes in one of p drive states, where n greater than m and pxe2x89xa72. The first communication device may include drive circuitry within the output section connected to each of the m data output nodes in each of the p drive states dependent upon the binary data and in response to the first clock signal. The output section may not drive a given data output node in an additional xe2x80x9cnon-drivexe2x80x9d state. In the non-drive state, the output section may electrically decouple the drive circuitry from the given data output node dependent upon the binary data and in response to the first clock signal. In each of the p drive states and the non-drive state, a different amount of electrical current may flow through the two termination resistors coupled to the data input node corresponding to a given data output node such that a different electrical voltage level exists at the data input node. The different electrical voltage levels existing at the data input node in each of the p drive states and the non-drive state may differ by substantially equal amounts and may be associated with different logic levels.
The output section also drives the clock output node in one of q drive states dependent upon the binary clock signal, where qxe2x89xa71. When q=1, an additional termination resistor may be coupled between the clock input node and the second power supply voltage level, and the output section may electrically decouple drive circuitry from the clock output node in an additional xe2x80x9cnon-drivexe2x80x9d state as described above. The values of the one or more termination resistors coupled to the clock input node may be selected such that the input resistance at the clock input node is substantially equal to the characteristic impedance of the clock transmission line. In this case, signal reflections and distortion occurring within the clock transmission line are substantially reduced. Each of the q drive states causes a different amount of electrical current to flow through the termination resistor coupled to the clock input node such that a different electrical voltage level exists at the clock input node in each of the q drive states.
As in the third embodiment, the input section is configured to: (i) produce the binary clock signal from the electrical voltage levels existing at the clock input node, and ii) produce the n binary data signals from the electrical voltage levels existing at the m data input nodes in response to the binary clock signal.
The structures of the first and second embodiments described above may be used to implement a data transmission scheme which facilitates the generation of the second clock signal within the second communication device and the synchronization of the second clock signal to the first clock signal. A ternary data stream including ternary data is produced upon the transmission line as described above, wherein a voltage level transition occurs within the ternary data stream every cycle of the first clock signal. The first communication device may generate the ternary data in a manner which guarantees a voltage level transition upon the transmission line for every cycle of the first clock signal even when the logic levels of the binary data remain unchanged from one cycle of the first clock signal to the next. The second communication device may reproduce the binary data from the ternary signals of the ternary data stream received via the transmission line.
In a method for implementing the above data transmission scheme, control logic within an output section of the first communication device may encode the binary data to form the ternary data stream. The second communication device may receive the ternary data stream and synchronize the second clock signal to the first clock signal using the voltage level transitions occurring within the ternary data stream. Circuitry within an input section of the second communication device may be used to decode the ternary data within the ternary data stream in response to the second clock signal thereby reproducing the binary data from the ternary data signals.
It is noted that the data transmission scheme described above eliminates the need for a separate clock transmission line to convey the first clock signal from the first communication device to the second communication device. It is noted that the ternary signals produced using the data transmission scheme may be used to encode the first clock signal with binary data upon multiple transmission lines coupled between the first communication device and the second communication device such that reception of the first clock signal by the second communication device is ensured even in case of transmission line failure.